|
週次 |
日期 |
單元主題 |
|
第1週 |
2/18 |
Course Overview,
Digital System Design Introduction |
|
第2週 |
2/25 |
Fundamentals of Hardware Description Language |
|
第3週 |
3/04 |
Logic Design at Register Transfer Level |
|
第4週 |
3/11 |
Logic Design with Behavior Coding,
Design Validation |
|
第5週 |
3/18 |
Synthesizable Coding of Verilog |
|
第6週 |
3/25 |
Coding Style and Verification Tool |
|
第7週 |
4/01 |
Synthesis Tool Usage (1) |
|
第8週 |
4/08 |
Complexity Management and Performance Improvement |
|
第9週 |
4/15 |
Midterm Exam |
|
第10週 |
4/22 |
Synthesis Tool Usage (2) |
|
第11週 |
4/29 |
Design Issues for MIPS
Processor (1) |
|
第12週 |
5/06 |
Design Issues for MIPS
Processor (2) |
|
第13週 |
5/13 |
Demo 952 Project Result |
|
第14週 |
5/20 |
Un-defined |
|
第15週 |
5/27 |
Project Check Point |
|
第16週 |
6/03 |
Break |
|
第17週 |
6/10 |
Project Demo |
|
第18週 |
6/17 |
Score Review |